Features of LPC2148
- Architecture: ARM v4T
- Processor: ARM7-TDMI-S
- Instructions: 32-bit ARM and 16-bit Thumb
- Debug support: RT EmbeddedICE, Embedded Trace interface
- Static RAM: 32 KB
- (On-chip)Additional: 8 KB for USB DMA
- Flash Program: 512 KB
- Mem.(On-chip)Programming: ISP/IAP via on-chip boot-loader program
- GPIO No. of pins: up to 45 (fast GPIO lines, 5V tolerant), Configurable to fast GPIO
- External Interrupts: Four; No. of pins: Nine
- Interrupts Sensitivity: Rising/falling edge or low/high level sensitive
- No. of Timers: Two, 32-bit
- Timer/Counter Operation: Counter or timer operation
- Compare & Capture: Four channels for each timer
- PWM No. of outputs: 6 single edge / 3 double edge controlled or mix; If not enabled: Used as a standard 32-bit timer/counter
- Watchdog Timer: 32-bit counter, divide by 4 fixed pre-scaler
- Timer: Internally resets the chip
- RTC Features: Maintains calendar, clock
- Provides Seconds, Minutes, Hours, day of week, day of Month, Month, day of Year, Year.
- Consumes very low power
- Dedicated power pin, can use battery
- Uses dedicated 32 kHz clock
- No. of ADC: Two, Successive approximation type
- No. of channel: 14 (ADC0 – 6 channels, ADC1 – 8 channels)
- ADC Resolution: 10-bit
- Conversion time: 2.44 s per channel
- VREF: >2.5V, <3.3 V
- No. of DAC: One
- DAC Resolution: 10-bit
- VREF : 3.3 V
- UART
- No. of channels: Two (16C550 compliant), UART0 and UART1
- Modem Interface: UART1 with full modem interface
- SPI
- No. of channels: One Full Duplex, Multiple master and slaves support
- SSP Compatibility: Motorola SPI, 4-wire TI SSI
- I2C No. of buses: Two
- USB USB ports: One
- Compliant: USB 2.0
- Data transfer rate: Full-speed (12 Mbps)
- Controller: USB Device
- Special feature: 2 KB endpoint RAM
- Package LQFP64 (Low profile Quad Flat Package)
- 128-bit memory interface
- 60 MHz operation
- PLL, VIC, Power Control
Architecture
Block Diagram
Pins & Signals
- LQFP64 package
- 64 (physical) pins
- Multiple functions assigned
- By default I/O function
- Power supply, ground, osc pins not multiplexed
System Control Block
Phase Locked Loop (PLL)
- LPC214x has two PLLs: PLL0 and PLL1
- PLL0 is used to generate clock for CPU (CCLK) & peripherals (PCLK)
- PLL1 is used for USB
- It uses crystal oscillator input frequency (FOSC) 10–25 MHz and generates output up to 60 MHz
- Parameters m & p determine output frequency, CCLK = m x FOSC
- In the feedback path of PLL there is current controlled osc (CCO) whose frequency should be kept within 156 – 320 MHz.
Computing m and p values for generating CCLK of 60 MHz from FOSC 12 MHz
- m = CCLK/FOSC = 60/12 = 5
- If p is chosen to be 2, CCO (= 2 x p x 60) is within 156 – 320 MHz.
PLL Registers
- PLLxCON – Controls PLL activation; used to enable and connect PLL
- PLLxCFG – Multiplier value (bits [4:0]) and divider value (bits [6:5] are configured
- PLLxSTAT – Shows current enable & connect status, m & p values, lock status
- PLLxFEED – Writing feed sequence, i.e. ‘0xAA’ and ‘0x55’ in sequence, to this register– It enables changes made to PLLCON, PLLCFG registers to take effect APBDIV – Sets PCLK freq to 1/4, same or 1/2 of CCLK (by writing 0x00, 0x01, 0x02)
PLL configuration sequence
- Determine m and p values for desired CCLK and PCLK from FOSC
- Enter (m-1) in bits [4:0] and enter 00/01/10/11 for p values 1/2/4/8 in bits [6:5] of PLLCFG register.
- Enable PLL using PLLCON register (by setting bit[0]).
- Issue feed sequence, i.e. write constants 0xAA, 0x55 into PLLFEED reg
- Wait for PLL to lock (by checking bit[10],
- Connect & enable PLL using PLLCON reg. (by setting bits[1:0])
- Issue again feed sequence
Examples
- Configuring PLL0 for generating 60 MHz CCLK from 12 MHz FOSC multiplier = CCLK / FOSC = 60 / 12 = 5; (m-1) = 4 is placed in bits [4:0]
- ‘p’ is chosen as 2, since CCO (= 2 x p x 60) is to be within 156 – 300 MHz
Enabling but not connecting PLL0, enabling and connecting:
- Bit [0] of PLL0CON register is set for only enabling and bits[1:0] are set for enabling and connecting.
- PLL0CON = 0x01; // enable PLL but not connect
- PLL0CON = 0x03; // enable PLL and connect
Issue of PLL feed sequence:
- PLL0FEED = 0xAA; // first fixed value
- PLL0FEED = 0x55; // second fixed value
Checking PLL0 lock status & waiting till PLL0 locks onto the target frequency:
PLOCK, the bit [10] of PLL0STAT register, is polled and checked for lock status.
PLOCK = 0x40;
while(!(PLLSTAT & PLOCK)); // poll lock status & wait till PLL0 locks
VPB Divider
Programming APB divider for desired PCLK frequency:
Value 0x00, 0x01 or 0x02 in APBDIV register sets the PCLK frequency to one-fourth, same as or half of CCLK frequency.
APBDIV = 0x02 // set PCLK frequency to (CCLK/2)
Memory Map
Draw & Explain the memory organization of LPC2148 (March-2018) - 5 Marks
Figures shows different views of the peripheral address space. Both the AHB and APB peripheral areas are 2 megabyte spaces which are divided up into 128 peripherals. Each peripheral space is 16 kilobytes in size. This allows simplifying the address decoding for each peripheral. All peripheral register addresses are word aligned (to 32-bit boundaries) regardless of their size. This eliminates the need for byte lane mapping hardware that would be required to allow byte (8-bit) or half-word (16-bit) accesses to occur at smaller boundaries. An implication of this is that word and half-word registers must be accessed all at once. For example, it is not possible to read or write the upper byte of a word register separately. AHB section is 128 x 16 kB blocks (totaling 2 MB). APB section is 128 x 16 kB blocks (totaling 2MB).
General Purpose Input Output (GPIO)
Pins not selected for peripheral functions are GP I/O port pin
I/O port pins dynamically configured as input/output using GPIO reg.
I/O port pins dynamically configured as input/output using GPIO reg.
Two sets of GPIO registers: Both control same I/O pins
- One set on APB, provides legacy (normal) GPIO functionality
- Another set on ARM local bus, provides enhanced (fast) GPIO function
- In enhanced mode, registers are byte addressable
- Includes mask registers to treat bits in groups
GPIO registers
- IOxPIN – To get logic value on a I/O pin
- IOxSET – To set an output configured pin (by writing 1 in corresponding bit)
- IOxCLR - To clear an output configured pin (by writing 1 in corresponding bit)
- IOxDIR – To select input /output function (by placing 0/1) for an I/O pin
- (x = 0/1, i.e. Port-0 or Port-1)
Examples
Configuring & initializing GPIO pin:
PINSEL1=0x00000000; // configure pins from P0.16 to P0.19 as GPIO
IO0DIR=0x000F0000; // set pins P0.16 – P0.19 to output function
IO0SET=0x000F0000 ; // set pins P0.16 & P0.18 of Port-0 HIGH
IO0CLR=0x000F0000 ; // reset logic level of pin P0.16 of Port-0 LOW
IO0DIR=0x000F0000; // set pins P0.16 – P0.19 to output function
IO0SET=0x000F0000 ; // set pins P0.16 & P0.18 of Port-0 HIGH
IO0CLR=0x000F0000 ; // reset logic level of pin P0.16 of Port-0 LOW
Pin Connect Block
Features
- 64 pins are attached to two 32-bit I/O ports, Port-0 & Port-1.
- Port-0, Port-1 pins are designated as P0.0 – P0.31 & P1.0 - P1.31.
- Pins P0.24, P0.26, P0.27, P1.0-P1.15 are unavailable.
- Pin functions are multiplexed, up to 4 functions assigned to each pin.
- Port-0 pins multiplex peripheral pin, & comm. interface pin functions
- Port-1 pins multiplex JTAG interface, Trace function
- Advantages: keeps size small, adds more functionalities to devices
- Disadvantages: if functions not carefully selected, some can’t be availed
- Pin function select Registers: PINSEL0, PINSEL1, PINSEL2
- PINSEL0 selects functions of pins P0.0 to P0.15,
- PINSEL1 selects functions of pins P0.16 to P0.31
- PINSEL2 selects functions of pins P1.16 to P1.31
Pin function selection: Examples
- Configuring P0.0 and P0.1 of Port-0 as I/O pins for TxD0 and RxD0 functions of UART0 in ‘C’:
- PINSEL0=0x00000000; //clear bits[3:2], [1:0] of PINSEL0 register, hence assign P0.0, P0.1 general purpose I/O function
- PINSEL0=0x00000005; //place 01 in bits[3:2], [1:0] of PINSEL0 register which selects TxD0 for P0.0 & RxD0 for P0.1 pins
- For using DAC, select Aout function for P0.25 pin.
- PINSEL1=0X00080000...//place 10 into bits[19:18] of PINSEL1 reg.select Aout function for P0.25
Timer in LPC 2148
- No. of Timers : 2, (Timer0 and Timer1) n
- The LPC2148 has two functionally identical general purpose timers:
- Timer0 and Timer1.
- Both Timer/Counter with a programmable 32-bit Prescaler.
- Counter or Timer operation.
- Up to four 32-bit capture channels per timer, that can take a snapshot of the
- timer value when an input signal transitions. A capture event may also
- optionally generate an interrupt.
- Four 32-bit match registers that allow:
- Continuous operation with optional interrupt generation on match.
- Stop timer on match with optional interrupt generation.
- Reset timer on match with optional interrupt generation
- Up to four external outputs corresponding to match registers, with the following capabilities:
- Set low on match.
- Set high on match.
- Toggle on match.
- Do nothing on match.
- Capture Register:- As the name suggests it is used to Capture Input signal. When a transition event occurs on a Capture pin , it can be used to copy the value of TC into any of the 4 Capture Register or to genreate an Interrupt. Hence these can be also used to demodulated PWM signals.
- Match Register:-A Match Register is a Register which contains a specific value set by the user. When the Timer starts – every time after TC is incremented the value in TC is compared with match register. If it matches then it can Reset the Timer or can generate an interrupt as defined by the user. We are only concerned with match registers in this PPT.
Functional Block Diagram
- Timer Operation:
- Uses PCLK clock
- Prescale Counter (PC) increments on each PCLK clock input pulse o Prescale Register (PR) holds 32-bit value
- When PC = PR, increments Timer/Counter (TC) and resets PC o Hence, TC counting rate is controlled by PR
- Each timer has 4 capture channels, 4 capture inputs (CAPx.0-CAPx.3)
- A transition on capture input, copies TC value into Capture Reg (CR)
- Can optionally generate interrupt also
- CCR configures capturing event (rising, falling or both edges)
- Each timer has 4 match channels, 4 match outputs (MATx.0-MATx.3)
- For each match channel, there is a MR that holds 32-bit value
- When TC = MR, an event (reset or stop TC, generate int) is triggered o MCR configures type of event to generate
Timer Registers
- Timer Counter (TC): Incremented when PC = PR
- Timer Control Register (TCR): Enables / disables, resets TC
- Prescale Register (PR): Holds max value for PC to count up to. Controls counting rate
- Prescale Counter (PC): Increments on every PCLK clock
- Capture Registers 0 – 3: Transition on cap inputs copy TC into respective reg
- Capture Control Register (CCR): Prescribes active event (rising/falling edge), int
- Match Registers 0 – 3 (MR): Holds a value, matched with TC, matching triggers event
- Match Control Register (MCR): Prescribes action (enabling/ disabling interrupt generation, resetting/disabling TC, or stopping TC and PC) to be triggered on match
- Count Control Register (CTCR): Selects Timer or Counter mode;
- Interrupt Register (IR): Has 4 bits for match interrupt, 4 bits for capture interrupt.When interrupt occurs corresponding bit is set. Writing high in a bit resets corresponding interrupt
Programming Timer Registers
The registers for a typical application are configured in the following order:
- TxCTCR and TxIR registers are programmed.
- TxPR and TxMRy are initialized with appropriate values.
- TxMCR and TxCCR are programmed.
- TC and PR are reset by programming TxTCR register.
- Timer is enabled by programming TxTCR register.
Applications
PWM, data acquisition, measurements of freq, speed, velocity, position
Timer Calculations
How to calculate value of prescaler ?
